A Case Study of Hybrid Dataflow and Shared-Memory Programming Models: Dependency-Based Parallel Game Engine

AMMC: Advanced Multi-Core Memory Controller

Advanced Pattern based Memory Controller for FPGA based HPC applications

Architectural Support for Fair Reader-Writer Locking

scholarly article published December 2010

Atomic quake

CRC-Based Memory Reliability for Task-Parallel HPC Applications

Circuit design of a dual-versioning L1 data cache

Circuit design of a dual-versioning L1 data cache for optimistic concurrency

Clock gate on abort: Towards energy-efficient hardware Transactional Memory

DaSH: A benchmark suite for hybrid dataflow and shared memory programming models

DaSH: a benchmark suite for hybrid dataflow and shared memory programming models

DeTrans: Deterministic and Parallel execution of Transactions

article published in 2014

Debugging programs that use atomic blocks and transactional memory

Debugging programs that use atomic blocks and transactional memory

Determinism at Standard-Library Level in TM-Based Applications

Discovering and understanding performance bottlenecks in transactional applications

Dynamic transaction coalescing

Dynamic-vector execution on a general purpose EDGE chip multiprocessor

Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory

EVX: Vector execution on low power EDGE cores

EazyHTM

EcoTM: Conflict-aware Economical Unbounded Hardware Transactional Memory

Enhancing the performance of assisted execution runtime systems through hardware/software techniques

Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi

FIMSIM: A fault injection infrastructure for microarchitectural simulators

Fault-Tolerant Protocol for Hybrid Task-Parallel Message-Passing Applications

From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype

Future Vector Microprocessor Extensions for Data Aggregations

Hardware Round-Robin Scheduler for Single-ISA Asymmetric Multi-core

Hardware Transactional Memory with Operating System Support, HTMOS

Hardware transactional memory with software-defined conflicts

Hybrid Transactional Memory with Pessimistic Concurrency Control

Integrating Dataflow Abstractions into the Shared Memory Model

Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors

Kernel-to-User-Mode Transition-Aware Hardware Scheduling

MAPC: Memory access pattern based controller

Marriage Between Coordinated and Uncoordinated Checkpointing for the Exascale Era

Multithreaded software transactional memory and OpenMP

NanoCheckpoints: A Task-Based Asynchronous Dataflow Framework for Efficient and Scalable Checkpoint/Restart

Nebelung: Execution Environment for Transactional OpenMP

PAMS: Pattern Aware Memory System for embedded systems

POSTER

PVMC: Programmable Vector Memory Controller

Performance and Energy Efficient Hardware-Based Scheduler for Symmetric/Asymmetric CMPs

Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders

Profile-guided transaction coalescing—lowering transactional overheads by merging transactions

Profiling and Optimizing Transactional Memory Applications

Programmer-directed partial redundancy for resilient HPC

QuakeTM

RMS-TM

Rapid Development of Error-Free Architectural Simulators Using Dynamic Runtime Testing

article

Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model

Reimagining Heterogeneous Computing: a Functional Instruction Set Architecture (F-ISA) Computing Model

Resource-bounded multicore emulation using Beefarm

Runtime-Aware Architectures

STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems

Spatial Support Vector Regression to Detect Silent Errors in the Exascale Era

Stand-Alone Memory Controller for Graphics System

Supporting stateful tasks in a dataflow graph

scholarly article

SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory

article published in 2011

TM-dietlibc: A TM-aware Real-World System Library

TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System

Taking the heat off transactions: Dynamic selection of pessimistic concurrency control

The limits of software transactional memory (STM)

Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core

Transactional Memory and OpenMP

Transactional Memory: An Overview

Turbocharging boosted transactions or

Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators

article

Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory

VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors

Vector Extensions for Decision Support DBMS Acceleration

article published in 2012

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications

artículo científico publicado en 2022

WormBench