A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation of a Space Case Study

A Quantitative Analysis of OS Noise

A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-threaded Hard Real-Time Tasks

A Two-Level Load/Store Queue Based on Execution Locality

A hard real-time capable multi-core SMT processor

AHRB: A high-performance time-composable AMBA AHB bus

Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded Systems

scientific article published on 24 January 2023

Achieving timing composability with measurement-based probabilistic timing analysis

Adapting cache partitioning algorithms to pseudo-LRU replacement policies

An Analyzable Memory Controller for Hard Real-Time CMPs

Assessing the suitability of the NGMP multi-core processor in the space domain

Balancing HPC applications through smart allocation of resources in MT processors

Bus designs for time-probabilistic multicore processors

Characterizing Power and Temperature Behavior of POWER6-Based System

Characterizing the resource-sharing levels in the UltraSPARC T2 processor

DReAM: Per-Task DRAM Energy Metering in Multicore Systems

DTM: Degraded Test Mode for Fault-Aware Probabilistic Timing Analysis

Deconstructing bus access control policies for Real-Time multicores

Dynamic Cache Partitioning Based on the MLP of Cache Misses

Dynamic and execution views to improve validation, testing, and optimization of autonomous driving software

artículo científico publicado en 2023

Efficient Cache Designs for Probabilistically Analysable Real-Time Systems

article published in 2014

Fair CPU time accounting in CMP+SMT processors

FlexDCP

GPU Devices for Safety-Critical Systems: A Survey

artículo científico publicado en 2022

Hardware support for WCET analysis of hard real-time multicore systems

Hardware support for accurate per-task energy metering in multicore systems

Heart of Gold: Making the Improbable Happen to Increase Confidence in MBPTA

Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation

Hybrid high-performance low-power and ultra-low energy reliable caches

IA^3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems

ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs

Increasing Testing Robustness of GPU Software in Embedded Critical Systems

artículo científico publicado en 2024

Increasing confidence on measurement-based contention bounds for real-time round-robin buses

Introduction to partial time composability for COTS multicores

Load balancing using dynamic cache allocation

MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors

scholarly article published September 2008

MLP-Aware Dynamic Cache Partitioning

Measurement-Based Probabilistic Timing Analysis and Its Impact on Processor Architecture

scholarly article published August 2014

Measurement-Based Probabilistic Timing Analysis for Multi-path Programs

Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study

Measuring Operating System Overhead on CMT Processors

Multi-level Unified Caches for Probabilistically Time Analysable Real-Time Systems

Multicore Resource Management

On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques

On the Problem of Evaluating the Performance of Multiprogrammed Workloads

On the Problem of Minimizing Workload Execution Time in SMT Processors

On the Safe Deployment of Matrix Multiplication in Massively Parallel Safety-Related Systems

artículo científico publicado en 2022

On the convergence of mainstream and mission-critical markets

On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments

Online Prediction of Applications Cache Utility

Optimal task assignment in multithreaded processors

PACO

PUB: Path Upper-Bounding for Measurement-Based Probabilistic Timing Analysis

Per-task Energy Accounting in Computing Systems

Power and performance aware reconfigurable cache for CMPs

Power and thermal characterization of POWER6 system

RVC

scholarly article published in 2011

RVC-based time-predictable faulty caches for safety-critical systems

RunPar

Sensible Energy Accounting with Abstract Metering for Multicore Systems

Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation

Software-Controlled Priority Characterization of POWER5 Processor

Speeding up Static Probabilistic Timing Analysis

Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors

Thread to Core Assignment in SMT On-Chip Multiprocessors

Thread to strand binding of parallel network applications in massive multi-threaded systems

Thread to strand binding of parallel network applications in massive multi-threaded systems

Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems

Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments

Timing effects of DDR memory systems in hard real-time multicore architectures

Towards improved survivability in safety-critical systems

Trends and techniques for energy efficient architectures

scholarly article published September 2010

Using Randomized Caches in Probabilistic Real-Time Systems

article published in 2009

Vector Extensions in COTS Processors to Increase Guaranteed Performance in Real-Time Systems

artículo científico publicado en 2022

parMERASA -- Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability

Kilo-Instruction Processors: Overcoming the Memory Wall

artículo científico publicado en 2005