130 and 90nm CMOS technologies for detector front-end applications

28 nm CMOS analog front-end channels for future pixel detectors

scientific article published in 2023

2D and 3D CMOS MAPS with high performance pixel-level signal processing

scholarly article by Gianluca Traversi et al published February 2011 in Nuclear Instruments and Methods in Physics Research

2D and 3D thin pixel technologies for the Layer0 of the SuperB Silicon Vertex Tracker

3D DNW MAPS for high resolution, highly efficient, sparse readout CMOS detectors

65 nm CMOS analog front-end for pixel detectors at the HL-LHC

65-nm CMOS Front-End Channel for Pixel Readout in the HL-LHC Radiation Environment

A 3D Vertically Integrated Deep N-Well CMOS MAPS for the SuperB Layer0

A 3D deep n-well CMOS MAPS for the ILC vertex detector

A 4096-pixel MAPS device with on-chip data sparsification

A 65-nm CMOS Prototype Chip With Monolithic Pixel Sensors and Fast Front-End Electronics

article published in 2012

A bilinear analog compressor to adapt the signal dynamic range in the AUGER fluorescence detector

A new approach to the design of monolithic active pixel detectors in triple well CMOS technology

A novel monolithic active pixel detector in triple well CMOS technology with pixel level analog processing

article published in 2006

A study for the detection of ionizing particles with phototransistors on thick high-resistivity silicon substrates

Active pixel sensors with enhanced pixel-level analog and digital functionalities in a 2-tier 3D CMOS technology

Advances in the development of pixel detector for the SuperB Silicon Vertex Tracker

Advantages of a vertical integration process in the design of DNW MAPS

Analog design criteria for high-granularity detector readout in the 65 nm CMOS technology

Assessment of a Low-Power 65 nm CMOS Technology for Analog Front-End Design

Beam test results for the SuperB-SVT thin striplet detector

Beam test results of different configurations of deep N-well MAPS matrices featuring in pixel full signal processing

scholarly article by Eugenio Paoloni et al published February 2011 in Nuclear Instruments and Methods in Physics Research

Beam-test results of 4k pixel CMOS MAPS and high resistivity striplet detectors equipped with digital sparsified readout in the Slim5 low mass silicon demonstrator

CHIPIX65: Developments on a new generation pixel readout ASIC in CMOS 65 nm for HEP experiments

CMOS MAPS in a Homogeneous 3D Process for Charged Particle Tracking

CMOS MAPS in a homogeneous 3D process for charged particle tracking

CMOS MAPS with pixel level sparsification and time stamping capabilities for applications at the ILC

CMOS technologies in the 100nm range for rad-hard front-end electronics in future collider experiments

Channel hot carrier stress on irradiated 130-nm NMOSFETs: Impact of bias conditions during X-ray exposure

article

Characterization of bandgap reference circuits designed for high energy physics applications

Charge signal processors in sparse readout CMOS MAPS and hybrid pixel sensors for the SuperB Layer0

Comparison of ionizing radiation effects in 0.18 and 0.25 μm cmos technologies for analog applications

article published in 2003

Comprehensive Study of Total Ionizing Dose Damage Mechanisms and Their Effects on Noise Sources in a 90 nm CMOS Technology

Correction to "Selection criteria for F and N-channel JFETs as input elements in low-noise radiation-hard charge preamplifiers"

scholarly article published in IEEE Transactions on Nuclear Science

Deep n-well MAPS in a 130nm CMOS technology: Beam test results

Design Optimization of Charge Preamplifiers With CMOS Processes in the 100 nm Gate Length Regime

Design and Performance of Analog Circuits for DNW-MAPS in 100-nm-scale CMOS Technology

Design and Performance of a DNW CMOS Active Pixel Sensor for the ILC Vertex Detector

Design and TCAD simulation of planar p-on-n active-edge pixel sensors for the next generation of FELs

Design and TCAD simulations of planar active-edge pixel sensors for future XFEL applications

Design and characterization of integrated front-end transistors in a micro-strip detector technology

article

Design and test of clock distribution circuits for the Macro Pixel ASIC

article published in 2016

Design criteria for low noise front-end electronics in the 0.13μm CMOS generation

Design of Time Invariant Analog Front-End Circuits for Deep N-Well CMOS MAPS

Design of bandgap reference circuits in a 65 nm CMOS technology for HL-LHC applications

Design of low-power, low-voltage, differential I/O links for High Energy Physics applications

Development of 130nm CMOS Monolithic Active Pixels with In-pixel Signal Processing

scholarly article published 2006

Development of deep N-well MAPS in a 130 nm CMOS technology and beam test results on a 4k-pixel matrix with digital sparsified readout

artículo científico

Development of deep N-well monolithic active pixel sensors in a CMOS technology

Development of the DEPFET Sensor With Signal Compression: A Large Format X-Ray Imager With Mega-Frame Readout Capability for the European XFEL

Dynamic Compression of the Signal in a Charge Sensitive Amplifier: From Concept to Design

Effects of Substrate Thinning on the Properties of Quadruple Well CMOS MAPS

Effects of γ-rays on JFET devices and circuits fabricated in a detector-compatible process

Erratum to: “Low-noise design criteria for detector readout systems in deep submicron CMOS technology”

scholarly article published in Nuclear Instruments and Methods in Physics Research

Evaluation of the radiation tolerance of 65 nm CMOS devices for high-density front-end electronics

Experimental studies of the noise properties of a deep submicron CMOS process

Experimental study and modeling of the white noise sources in submicron Pand N-MOSFETs

FSSR2, a Self-Triggered Low Noise Readout Chip for Silicon Strip Detectors

FSSR2, a Self-Triggered Low Noise Readout Chip for Silicon Strip Detectors

Fast analog front-end for the readout of the SuperB SVT inner Layers

Feasibility studies of microelectrode silicon detectors with integrated electronics

Fermilab silicon strip readout chip for BTeV

First generation of deep n-well CMOS MAPS with in-pixel sparsification for the ILC vertex detector

First prototype of a silicon microstrip detector with the data-driven readout chip FSSR2 for a tracking-based trigger system

First results from the characterization of a three-dimensional deep N-well MAPS prototype for vertexing applications

Forecasting noise and radiation hardness of CMOS front-end electronics beyond the 100nm frontier

Front-End Performance and Charge Collection Properties of Heavily Irradiated DNW MAPS

Front-end electronics for pixel sensors

article published in 2001

Front-end electronics in a 65nm CMOS process for high density readout of pixel sensors

Front-end performance and charge collection properties of heavily irradiated DNW MAPS

Gamma-ray response of SOI bipolar junction transistors for fast, radiation tolerant front-end electronics

article

Gate Current Noise in Ultrathin Oxide MOSFETs and Its Impact on the Performance of Analog Front-End Circuits

High accuracy injection circuit for pixel-level calibration of readout electronics

High accuracy injection circuit for the calibration of a large pixel sensor matrix

High precision injection circuit for in-pixel calibration of a large sensor matrix

Impact of Lateral Isolation Oxides on Radiation-Induced Noise Degradation in CMOS Technologies in the 100-nm Regime

Impact of gate-leakage current noise in sub-100 nm CMOS front-end electronics

In-pixel conversion with a 10 bit SAR ADC for next generation X-ray FELs

Instrumentation for noise measurements on CMOS transistors for fast detector preamplifiers

article

Integrated front-end electronics in a detector compatible process: source-follower and charge-sensitive preamplifier configurations

Introducing 65nm CMOS technology in low-noise read-out of semiconductor detectors

Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

Investigating degradation mechanisms in 130 nm and 90 nm commercial CMOS technologies exposed to up to 100 Mrad ionizing radiation dose

JFET front-end circuits integrated in a detector-grade silicon substrate

JFET preamplifiers with different reset techniques on detector-grade high-resistivity silicon

Latest results of the R&D on CMOS MAPS for the Layer0 of the SuperB SVT

Low-noise design criteria for detector readout systems in deep submicron CMOS technology

Low-noise readout channel with a novel dynamic signal compression for future X-FEL applications

Low-power clock distribution circuits for the Macro Pixel ASIC

article published in 2015

Mechanisms of Noise Degradation in Low Power 65 nm CMOS Transistors Exposed to Ionizing Radiation

article

Minimum noise design of charge amplifiers with CMOS processes in the 100 nm feature size range

Monolithic pixel detectors in a CMOS technology with sensor level continuous time charge amplification and shaping

Noise Behavior of a 180 nm CMOS SOI Technology for Detector Front-End Electronics

Noise Characterization of 130 nm and 90 nm CMOS Technologies for Analog Front-end Electronics

Noise Performance of 0.13$mu$m CMOS Technologies for Detector Front-End Applications

Noise Performances of 0.13 μm CMOS Technologies for Detector Front-end Applications

Noise analysis of NPN SOI bipolar transistors for the design of charge measuring systems

article

Non-Standard Approach to Charge Signal Processing in CMOS MAPS for Charged Particle Trackers

scholarly article

Novel active signal compression in low-noise analog readout at future X-ray FEL facilities

On-Chip Fast Data Sparsification for a Monolithic 4096-Pixel Device

Performance of a DNW CMOS active pixel sensor designed for the ILC Vertex Detector

Performance of a high accuracy injection circuit for in-pixel calibration of a large sensor matrix

Perspectives for low noise detector readout in a sub-quarter-micron CMOS SOI technology

PixFEL: Enabling technologies, building blocks and architectures for advanced X-ray pixel cameras at the next generation FELs

article published in 2014

PixFEL: developing a fine pitch, fast 2D X-ray imager for the next generation X-FELs

Pixel readout ASIC with per pixel digitization and digital storage for the DSSC detector at XFEL

Pixel-Level Charge and Current Injection Circuit for High Accuracy Calibration of the DSSC Chip at the European XFEL

Pixel-level continuous-time analog signal processing for 130nm CMOS MAPS

scholarly article by Gianluca Traversi et al published March 2007 in Nuclear Instruments and Methods in Physics Research

Proposal of a data sparsification unit for a mixed-mode MAPS detector

Proton-induced damage in JFET transistors and charge preamplifiers on high-resistivity silicon

article

Radiation Tolerance of Devices and Circuits in a 3D Technology Based on the Vertical Integration of Two 130-nm CMOS Layers

Radiation effects on the noise parameters of a 0.18 μm CMOS technology for detector front-end applications

Radiation hardness perspectives for the design of analog detector readout circuits in the 0.18-μm CMOS generation

Radiation hardness test of FSSR, a multichannel, mixed signal chip for microstrip detector readout

Recent development on triple well 130 nm CMOS MAPS with in-pixel signal processing and data sparsification capability

scholarly article published 2007

Recent developments in 130 nm CMOS monolithic active pixel detectors

Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker

Recent progress in the development of 3D deep n-well CMOS MAPS

Recent results from the development of silicon detectors with integrated electronics

Resolution Limits in 130 nm and 90 nm CMOS Technologies for Analog Front-End Applications

Resolution limits achievable with CMOS front-end in X- and γ-ray analysis with semiconductor detectors

Response of SOI bipolar transistors exposed to /spl gamma/-rays under different dose rate and bias conditions

article

Review of radiation damage studies on DNW CMOS MAPS

Review of radiation effects leading to noise performance degradation in 100 - nm scale microelectronic technologies

SLIM5 beam test results for thin striplet detector and fast readout beam telescope

Selection criteria for P- and N-channel JFETs as input elements in low-noise radiation-hard charge preamplifiers

Submicron CMOS technologies for low-noise analog front-end circuits

Survey of noise performances and scaling effects in deep submicrometer CMOS devices from different foundries

TID Effects in Deep N-Well CMOS Monolithic Active Pixel Sensors

TID effects in deep N-well CMOS monolithic active pixel sensors

TID-Induced Degradation in Static and Noise Behavior of Sub-100 nm Multifinger Bulk NMOSFETs

The Apsel65 front-end chip for the readout of pixel sensors in the 65 nm CMOS node

The DSSC pixel readout ASIC with amplitude digitization and local storage for DEPFET sensor matrices at the European XFEL

The PixFEL project: Progress towards a fine pitch X-ray imaging camera for next generation FEL facilities

The SLIM5 low mass silicon tracker demonstrator

article published in 2010

The SuperB silicon vertex tracker

The associative memory for the self-triggered SLIM5 silicon telescope

The design of fast analog channels for the readout of strip detectors in the inner layers of the SuperB SVT

The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector

The front-end chip of the SuperB SVT detector

The high rate data acquisition system for the SLIM5 beam test

article published in 2010

The readout of the LHC beam luminosity monitor: accurate shower energy measurements at a repetition rate

The superB silicon vertex tracker

Thin pixel development for the Layer0 of the SuperB Silicon Vertex Tracker

Thin pixel development for the SuperB silicon vertex tracker

Time invariant analog processors for monolithic deep n-well CMOS pixel detectors

Total Ionizing Dose effects in 130-nm commercial CMOS technologies for HEP experiments

Total ionizing dose effects on the analog performance of a 0.13μm CMOS technology

Total ionizing dose effects on the noise performances of a 0.13 /spl mu/m CMOS technology

Triple Well CMOS Active Pixel Sensor with In-Pixel Full Signal Analog

Vertical integration approach to the readout of pixel detectors for vertexing applications

Vertically integrated deep N-well CMOS MAPS with sparsification and time stamping capabilities for thin charged particle trackers

Vertically integrated monolithic pixel sensors for charged particle tracking and biomedical imaging