A Survey of Near-Data Processing Architectures for Neural Networks

artículo científico publicado en 2022

An Energy-Efficient Memory Unit for Clustered Microarchitectures

Control-Flow Independence Reuse via Dynamic Vectorization

Cross-layer system reliability assessment framework for hardware faults

Design of complex circuits using the Via-Configurable transistor array regular layout fabric

article

Early Register Release for Out-of-Order Processors with RegisterWindows

article published in 2007

Efficient interconnects for clustered microarchitectures

Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study

article

Hardware schemes for early register release

Improving latency tolerance of multithreading through decoupling

K-D Bonsai: ISA-Extensions to Compress K-D Trees for Autonomous Driving Tasks

artículo científico publicado en 2023

Late allocation and early release of physical registers

Leveraging Register Windows to Reduce Physical Registers to the Bare Minimum

article published in 2010

Lifetime-sensitive modulo scheduling in a production environment

Memory bank predictors

Modulo scheduling with reduced register pressure

On-chip interconnects and instruction steering schemes for clustered microarchitectures

scholarly article by Joan-M. Parcerisa et al published February 2005 in IEEE Transactions on Parallel and Distributed Systems

Quantitative characterization of the software layer of a HW/SW co-designed processor

ReDy: A Novel ReRAM-centric Dynamic Quantization Approach for Energy-efficient CNNs

artículo científico publicado en 2024

SHARP: An Adaptable, Energy-Efficient Accelerator for Recurrent Neural Networks

artículo científico publicado en 2022

Selective predicate prediction for out-of-order processors

VCTA: A Via-Configurable Transistor Array regular fabric

article

δLTA: Decoupling Camera Sampling from Processing to Avoid Redundant Computations in the Vision Pipeline

artículo científico publicado en 2023