2D and 3D thin pixel technologies for the Layer0 of the SuperB Silicon Vertex Tracker

A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint

A Preliminary Study about SEU Effects on Programmable Interconnections of SRAM-based FPGAs

A XOR-based associative memory block in 28 nm CMOS for interdisciplinary applications

A digital self-calibration circuit for absolute optical rotary encoder microsystems

A digital self-calibration circuit for optical rotary encoder microsystems

A fast hardware tracker for the ATLAS trigger system

A low-power and high-density Associative Memory in 28 nm CMOS technology

A multi-megarad, radiation hardened by design 512 kbit SRAM in CMOS technology

A multiplierless decimation filter for ΣΔ A/D conversion

A new XOR-based Content Addressable Memory architecture

A new variable-resolution Associative Memory for high energy physics

A radiation hardened 512 kbit SRAM in 180 nm CMOS technology

A radiation hardened by design charge pump for flash memories

A radiation hardened static RAM for high-energy physics experiments

A stochastic approach to crosstalk analysis in mixed-signal ICs

A stochastic model of digital switching noise

A subthreshold, low-power, RHBD reference circuit, for earth observation and communication satellites

AM06: the Associative Memory chip for the Fast TracKer in the upgraded ATLAS detector

Advances in the development of pixel detector for the SuperB Silicon Vertex Tracker

An approximation algorithm for cofactoring-based synthesis

An automatically compensated readout channel for rotary encoder systems

An integrated CMOS telephone line adapter

scholarly article by Oluf Alminde et al published April 1992 in Analog Integrated Circuits and Signal Processing

Analysis and Measurement of Crosstalk Effects on Mixed-Signal CMOS ICs With Different Mounting Technologies

Analytical expressions for noise and crosstalk voltages of the High Energy Silicon Particle Detector

Associative memory design for the fast track processor (FTK) at ATLAS

Automatic switching of substrate bias or well bias in CMOS-ICs

article

Beam test results for the SuperB-SVT thin striplet detector

Beam test results of different configurations of deep N-well MAPS matrices featuring in pixel full signal processing

scholarly article by Eugenio Paoloni et al published February 2011 in Nuclear Instruments and Methods in Physics Research

CHIPIX65: Developments on a new generation pixel readout ASIC in CMOS 65 nm for HEP experiments

CMOS front-end for optical rotary encoders

Characterisation of an Associative Memory Chip for high-energy physics experiments

Conducted emissions in a 40 nm CMOS test chip: The role of the ESD protections

article published in 2017

Crosstalk effects in mixed-signal ICs in deep submicron digital CMOS technology

Design considerations for analog blocks in mixed-signal CMOS ICs

Design methodology for low-power embedded microprocessors

Design methodology for low-power embedded microprocessors

Design of LVDS driver and receiver in 28 nm CMOS technology for Associative Memories

Design of a hardware track finder (Fast Tracker) for the ATLAS trigger

Design of a rad-hard library of digital cells for space applications

Design of rad-hard SRAM cells: A comparative study

Design tools for oversampled data converters: Needs and solutions

Digital switching noise as a stochastic process

Double-redundant design methodology to improve radiation hardness in pixel detector readout ICs

Dynamic characterisation of A/D converters using fast Walsh transform

Effects of digital switching noise on analog circuits performance

Efficient implementation of multiplier-free decimation filters for ΣΔ A/D conversion

Enhancement of the ATLAS trigger system with a hardware tracker finder FTK

Enhancing logic synthesis of switching lattices by generalized Shannon decomposition methods

Evaluating the impact of substrate noise on conducted EMI in automotive microcontrollers

Evaluating the impact of substrate on power integrity in industrial microcontrollers

Evaluation of epi layer resistivity effects in mixed-signal submicron CMOS integrated circuits

Evolution in the criteria that underlie the design of a monolithic preamplifier system for microstrip detectors

Evolutionary design and FPGA implementation of digital filters

Evolutionary design of hashing function circuits using an FPGA

Exploiting body biasing for leakage reduction: A case study

article

FTK: a Fast Track Trigger for ATLAS

Generation of Optimal Unit Distance Codes for Rotary Encoders through Simulated Evolution

HV-CMOS detectors for high energy physics: Characterization of BCD8 technology and controlled hybridization technique

HV-CMOS detectors in BCD8 technology

Heterogeneous computing system platform for high-performance pattern recognition applications

scholarly article published May 2017

Impact of package parasitics on crosstalk in mixed-signal ICs

Improvement of radiation tolerance in CMOS ICs through layout-oriented simulation

JFET-CMOS microstrip front-end

Latest results of the R&D on CMOS MAPS for the Layer0 of the SuperB SVT

Layout-oriented simulation of non-destructive single event effects in CMOS IC blocks

Logic Synthesis for Switching Lattices by Decomposition with P-Circuits

Low-Power, Subthreshold Reference Circuits for the Space Environment: Evaluated with γ-rays, X-rays, Protons and Heavy Ions

Model and verification of triple-well shielding on substrate noise in mixed-signal CMOS ICs

Next generation associative memory devices for the FTK tracking processor of the ATLAS experiment

Parametric amplifier based dynamic clocked comparator

Performance of the AMBFTK board for the FastTracker processor for the ATLAS detector upgrade

Population count circuits for Associative Memories: A comparison study

Power Distribution Network optimization for Associative Memories

Practical design considerations on adaptive controllers for PWM DC/DC converters

Properties of Digital Switching Currents in Fully CMOS Combinational Logic

Radiation-tolerant standard cell synthesis using double-rail redundant approach

Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker

Recent progress of RD53 Collaboration towards next generation Pixel Read-Out Chip for HL-LHC

Role of IC substrate and ESD protections in noise propagation: Design and modelling of dedicated test chip in 40 nm technology

Sigma-delta modulators for high-resolution and wide-band A/D converter applications

Signal processing for smart sensors

scholarly article

Single Event Transients and Pulse Quenching Effects in Bandgap Reference Topologies for Space Applications

Synthesis of P-circuits for logic restructuring

TOSCA: a simulator for switched-capacitor noise-shaping A/D converters

The Associative Memory Serial Link Processor for the Fast TracKer (FTK) at ATLAS

The Fast Track real time processor and its impact on muon isolation, tau and b-jet online selections at ATLAS

The FastTracker Real Time Processor and Its Impact on Muon Isolation, Tau and b-Jet Online Selections at ATLAS

The SuperB silicon vertex tracker

The front-end chip of the SuperB SVT detector

The start-up circuit for a low voltage bandgap reference

The superB silicon vertex tracker

Thin pixel development for the Layer0 of the SuperB Silicon Vertex Tracker

Thin pixel development for the SuperB silicon vertex tracker

Two-path structure for high performance sigma-delta modulators