A Framework for Uniformly Analyze and Mitigate Radiation-effects on FPGAs for Aerospace

artículo científico publicado en 2023

A Low-Cost Emulation System for Fast Co-verification and Debug

A New Algorithm for the Analysis of the MCUs Sensitiveness of TMR Architectures in SRAM-Based FPGAs

A New Fault Injection Approach for Testing Network-on-Chips

A New Hardware/Software Platform and a New 1/E Neutron Source for Soft Error Studies: Testing FPGAs at the ISIS Facility

A New Mitigation Approach for Soft Errors in Embedded Processors

A New Partial Reconfiguration-Based Fault-Injection System to Evaluate SEU Effects in SRAM-Based FPGAs

article by Luca Sterpone & M. Violante published August 2007 in IEEE Transactions on Nuclear Science

A New Soft-Error Resilient Voltage-Mode Quaternary Latch

A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs

A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGA's

A Novel Dual-Core Architecture for the Analysis of DNA Microarray Images

A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing

A Novel Robust Core for Detecting Node Failures in FPGA Clusters

artículo científico publicado en 2024

A graph-based representation of Gene Expression profiles in DNA microarrays

article

A new RC design for mixed-grain based dynamically reconfigurable architectures

A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs

article

A new decompression system for the configuration process of SRAM-based FPGAS

A new hardware architecture for performing the gridding of DNA microarray images

scholarly article published 2007

A new low-cost non intrusive platform for injecting soft errors in SRAM-based FPGAs

A new mitigation approach for soft errors in embedded processors

A new placement algorithm for the optimization of fault tolerant circuits on reconfigurable devices

A new reliability-oriented place and route algorithm for SRAM-based FPGAs

A new software tool for static analysis of SET sensitiveness in Flash-based FPGAs

A novel scalable and reconfigurable emulation platform for embedded systems verification

A scalable platform for run-time reconfigurable satellite payload processing

Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs

An Analysis Based on Fault Injection of Hardening Techniques for SRAM-Based FPGAs

An Analysis of SEU Effects in Embedded Operating Systems for Real-Time Applications

An Analytical Model of the Propagation Induced Pulse Broadening (PIPB) Effects on Single Event Transient in Flash-Based FPGAs

An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems

An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques

An error-detection and self-repairing method for dynamically and partially reconfigurable systems

An experimental analysis of a new mixed grain-based dynamically reconfigurable architecture

article published in 2006

An experimental analysis of hardening techniques for SRAM-based FPGAs

An integrated flow for the design of hardened circuits on SRAM-based FPGAs

Analysis and Clustering of MicroRNA Array: A New Efficient and Reliable Computational Method ⬇️

artículo científico publicado el 1 de enero de 2011

Analysis of SET Propagation in Flash-Based FPGAs by Means of Electrical Pulse Injection

Analysis of SET propagation in flash-based FPGAs by means of electrical pulse injection

Analysis of SEU effects in partially reconfigurable SoPCs

Analysis of the robustness of the TMR architecture in SRAM-based FPGAs

article by Luca Sterpone & M. Violante published October 2005 in IEEE Transactions on Nuclear Science

Analytical analysis of the MCUs sensitiveness of TMR architectures in SRAM-based FPGAs

artículo científico publicado en 2007

Assessing the Robustness of Real-Time Operating System on Soft Processor against Multiple Bit Upset

artículo científico publicado en 2023

Assessment of RISC-V Processor Suitability for Satellite Applications

scientific article published on 01 July 2024

Combined software and hardware techniques for the design of reliable IP processors

Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs

Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices

Differential gene expression graphs: A data structure for classification in DNA microarrays

article

Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture

Effectiveness of TMR-Based Techniques to Mitigate Alpha-Induced SEU Accumulation in Commercial SRAM-Based FPGAs

Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumulation in commercial SRAM-based FPGAs

Efficient estimation of SEU effects in SRAM-based FPGAs

Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs

Experimental Validation of a Tool for Predicting the Effects of Soft Errors in SRAM-Based FPGAs

Experimental analysis of SEL sensitiveness on Atmel MG2RT technology

Exploiting the debug interface to support on-line test of control flow errors

FPGA Qualification and Failure Rate Estimation Methodology for LHC Environments Using Benchmarks Test Circuits

artículo científico publicado en 2022

FPGA-based serial links for SuperB: Design Issues Vs. Radiation Tolerance

Fault Injection-based Reliability Evaluation of SoPCs

Fault injection analysis of transient faults in clustered VLIW processors

Gene expression reliability estimation through cluster-based analysis

article

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

Hybrid Fault Detection Technique: A Case Study on Virtex-II Pro's PowerPC 405

Hybrid soft error mitigation techniques for COTS processor-based systems

Latch-up test measurement for long duration space missions

Layout and Radiation Tolerance Issues in High-Speed Links

Layout and radiation tolerance issues in high-speed links for TDAQ systems

Layout-Aware Multi-Cell Upsets Effects Analysis on TMR Circuits Implemented on SRAM-Based FPGAs

Layout-aware multi-cell upsets effects analysis on TMR circuits implemented on SRAM-based FPGAs

Methodologies to Study Frequency-Dependent Single Event Effects Sensitivity in Flash-Based FPGAs

Microvesicles derived from adult human bone marrow and tissue specific mesenchymal stem cells shuttle selected pattern of miRNAs

artículo científico publicado en 2010

Monte Carlo Analysis of the Effects of Soft Errors Accumulation in SRAM-Based FPGAs

Multiple Errors Produced by Single Upsets in FPGA Configuration Memory: A Possible Solution

New Techniques for Improving the Performance of the Lockstep Architecture for SEEs Mitigation in FPGA Embedded Processors

article published in 2009

New evolutionary techniques for test-program generation for complex microprocessor cores

On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors

scholarly article by Davide Sabena et al published April 2014 in IEEE Transactions on Very Large Scale Integration Systems

On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors

On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

On the Static Cross Section of SRAM-Based FPGAs

On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications

On the development of Software-Based Self-Test methods for VLIW processors

article

On the evaluation of SEU sensitiveness in SRAM-based FPGAs

On the mitigation of SET broadening effects in integrated circuits

On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs

On the optimized generation of Software-Based Self-Test programs for VLIW processors

Online Test of Control Flow Errors: A New Debug Interface-Based Approach

Optimization of Self Checking FIR filters by means of Fault Injection Analysis

Partition-Based Faults Diagnosis of a VLIW Processor

Power Consumption Versus Configuration SEUs in Xilinx Virtex-5 FPGAs

Preface

ReCoM: A new Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications

scholarly article

Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications

Reliability Analysis of Microarchitectural Faults in GPGPU-based HPC Systems

artículo científico publicado en 2023

RoRA: a reliability-oriented place and route algorithm for SRAM-based FPGAS

Robustness analysis of soft error accumulation in SRAM-FPGAs using FLIPPER and STAR/RoRA

SEL-UP: A CAD tool for the sensitivity analysis of radiation-induced Single Event Latch-Up

SEU effects on power consumption in FPGAs

Scalable K-Nearest Neighbors Implementation using Distributed Embedded Systems

artículo científico publicado en 2024

Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders

Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs

Simulation-based analysis of SEU effects in SRAM-based FPGAs

Soft Errors in SRAM-FPGAs: A Comparison of Two Complementary Approaches

Soft errors in Flash-based FPGAs: Analysis methodologies and first results

Soft errors in SRAM-FPGAs: A comparison of two complementary approaches

Software and Hardware Techniques for SEU Detection in IP Processors

Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs

Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs

Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs

Using Benchmarks for Radiation Testing of Microprocessors and FPGAs